The present invention relates to a structure for mounting electronic components on a substrate by means of soldering, and more particularly to a method for mounting electronic components on a substrate through use of an Au—Sn eutectic alloy surface. The present invention also relates to a method for forming a solder surface appropriate as a surface on which electronic components, or the like, are to be mounted. The present invention can be utilized for electronic components of every description in which electronic components are mounted on a substrate by means of soldering; for example, a silicon interposer, an LED, optical components, and the like.
Solder containing Pb or Sn as the principal ingredient has hitherto been used as a joining material for mounting electronic components on a substrate. A lead-free solder alloy is also used. Conventionally, when electronic components are soldered onto a substrate through use of lead-free solder, electrode areas on the substrate are plated with gold (Au) or tin (Sn). Alternatively, a solder pellet made of an Au—Sn alloy has hitherto been used.
FIG. 1 shows an example related-art technique for mounting electronic components onto a substrate by means of soldering; namely, a case where a semiconductor chip is mounted on a substrate stage electrode with a cavity. In FIG. 1, reference numeral 1 designates an essentially-rectangular silicon substrate with a cavity. The substrate assumes such a shape that the center of the substrate is formed into a recessed cavity area 2 and that a frame-shaped projection is provided along edges of the cavity area. The center portion of the cavity area 2 is a semiconductor chip mount area 3. A stage electrode 4 is formed from copper in this area. A plurality of terminal electrodes 6 to be connected to a mounted semiconductor chip 5 by means of bonding wires (not shown), or the like, are formed from copper at predetermined intervals around the semiconductor chip mount section 3 in the cavity area 2. Rear surfaces of the terminal electrodes are formed as external connection terminals.
In order to mount the electronic component 5 on such a silicon substrate 1 with a cavity, mounting has hitherto been practiced according to the following method.
In FIG. 1A, the silicon substrate is subjected to drilling, or like processing, and the thus-processed substrate is etched so as to assume the shape of the cavity 2 having a recess in the center thereof. Holes are subjected to through-hole plating, or the like, to thus form the stage electrode 4 in the center of the cavity 2 and the plurality of terminal electrodes 6 around the electrode. Since the silicon substrate assumes the shape of a cavity, an interior surface of the recess cannot be smoothed well. As illustrated in an exaggerated manner, the surface of the stage electrode 4 and the surfaces of the terminal electrodes 6 assume an irregular shape.
The surface of the stage electrode 4 located in the center and the surfaces of the terminal electrodes 6 located around the stage electrode are coated with gold (Au) plating 7, respectively. Thus, coating the surface of the stage electrode 4 and the surfaces of the terminal electrodes 6 with the gold plating 7 is for the purpose of enhancing the adhesion between the semiconductor chip 5 and the stage electrode 4 and a joining between the terminal electrodes 6 and bonding wires (not shown).
In FIG. 1B, an Au—Sn solder pellet 8 is affixed to the stage electrode 4 coated with the gold (Au) plating 7. This Au—Sn solder pellet 8 is intended for enhancing a joining between the semiconductor chip 5 to be mounted and the stage electrode 4.
In FIG. 1C, the semiconductor chip 5 is mounted on the stage electrode 4 of the silicon substrate 1 by means of the Au—Sn solder pellet 8. Mounting of this semiconductor chip 5 is performed by means of reflow processing or by means of simultaneous heating of the semiconductor chip 5 and the electrode 4.
Subsequently, electrodes of the semiconductor chip 5 mounted on the silicon substrate 1 and the terminal electrodes 6 are connected together by means of bonding wires (not shown).
A related-art technique relevant to the present invention is described in JP-A-2006-35310. This related-art technique is intended for acquiring a lead-free solder alloy which is not susceptible to an adverse effect induced by reflow processing even when lead-free solder having a comparatively-high melting point is used as solder for mounting electronic components on a substrate and which can be preferably used in die bonding operation for bonding the inside of the electronic components. The lead-free solder contains 10 to 24.9 mass percents of Cu, 5 mass percents or more of Sb, and a residue made of Sn. The Sn content exceeds 70 mass percents. JP-A-2006-35310 also discloses that the solder is caused to contain a predetermined amount of one kind of element or more kinds of elements selected from the group comprising Ag, Au, and Pd along with Cu and that addition of Te to solder and addition of P or Ge are also preferable.
JP-A-2006-35310
As in the case of the related-art technique shown in FIG. 1, difficulty is encountered in manipulating a tool, such as a polishing jig, or the like, with regard to an interior surface of a cavity as in a silicon substrate with a cavity. When electronic components (semiconductor chips) are mounted on a stage electrode whose interior surface is difficult to smooth or on a substrate stage electrode having terminal electrodes, difficulty is encountered in smoothing a surface of the stage electrode or surfaces of the terminal electrodes. Hence, smoothing of the surfaces becomes insufficient, and there arises a problem of occurrence of poor adhesion between the mounted electronic components and the stage electrode. Solving these problems also produces another problem of a necessity for expensive means to smooth a semiconductor chip mount surface, such as plating of the stage electrode or the terminal electrodes with gold or use of an Au—Sn solder pellet for the stage electrode.
Even in relation to the lead-free solder alloy disclosed in the previously-described related-art technique (JP-A-2006-35310), electronic components cannot be mounted on a substrate whose surface is difficult to smooth, as in the case of the previously-described silicon substrate with a cavity, with superior adhesion.
Accordingly, the challenge to be met by the present invention is to provide a method for forming a solder surface which can be appropriately provided in a case where electronic components are mounted on a solder surface of a substrate, or the like, and which enables inexpensive formation of a smoothed solder surface formed from an Au—Sn eutectic alloy.
Moreover, the challenge to be met by the present invention is to provide a method for mounting electronic components on a substrate which enables appropriate mounting of electronic components by means of smoothing surfaces of stage electrodes onto which the electronic components are to be mounted respectively.